1. Field of the Invention
The present invention relates generally to the design and fabrication of integrated circuits (ICs) and, more specifically but not exclusively, to computer-aided design (CAD) tools for generating IC layouts.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention(s). Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.
An IC layout is a representation of an integrated circuit in terms of planar geometric shapes corresponding to various sub-circuits, such as functional blocks, interfaces, and/or individual circuit elements. Since the behavior and performance of an IC depends on the positions of and interconnections between its sub-circuits, a layout engineer aims to place and connect the sub-circuits on a chip so that certain criteria specifying, e.g., performance characteristics, manufacturability parameters, and geometric size are met. An IC layout is usually subjected to various verification procedures, with the two most-commonly used being the Design Rule Checking (DRC) and Layout Versus Schematic (LVS) analyses. After the layout is verified, it is translated into a suitable standard format, and the resulting files are then sent to a semiconductor foundry for fabricating the IC.
For relatively large ICs, e.g., having millions of gates, the process of producing a suitable IC layout involves analyzing many possible floorplans. With the CAD tools that are currently available on the market, this process can be relatively time consuming and cumbersome because it involves many manual tasks. For example, during early design phases, when gate-level netlists are not yet reasonably complete, a layout engineer might be forced to manually define black-box shapes in lieu of the missing netlists. Furthermore, most prior-art floor-planning tools do not work for pure register-transfer-level (RTL) descriptions, which disadvantageously prevents users from performing a floorplan analysis early in the design process.